Self-aligned Gate Jfets for Smart Mems -modeling, Design and Fabrication

Modeling, design, fabrication and characterization of Self-Aligned Gate JFET (SJFET) devices and circuits are reported. The problem of electrical isolation between devices on the same chip is solved through Self-Aligned Gate approach, enabling device integration at the application of standard bipolar discrete device technology (no epitaxy etc.). Therefore this approach offers several advantages compared to other isolation techniques (lower number of fabrication steps, lower process temperature budget, reduction of leakage problems, lower chip cost etc.) and is appropriate for application in microsystems. SJFETs are analyzed by 2D numerical device simulation. SJFET circuits are analyzed by device modeling based circuit simulation. SJFET differential amplifier circuit simulation is reviewed as an example. On the basis of modeling results, test SJFET structures were designed and fabricated. Measurements on test SJFET structures reveal reasonable agreement with modeling.